The thin silicon dies have been widely used in the three-dimensional integrated circuits (3DIC), stacked-die or wearable electronic packages to meet the requirements of small size, low-profile features, high-pin count, high performance, low-power consumption or even flexibility. The silicon wafers have to be ground to be relatively thin, typically from about 800 μm to 100 μm, or even to 10 μm. After the wafer thinning and sawing processes, the bending strength of dies cut from the wafers has to be determined for ensuring no reliability problems, mostly resulting from packaging process handling, reliability testing, and operations. The four-point bending (4PB) test is one of the common methods used for determining the bending strength of the silicon dies; however, this test is still problematic for testing the thin silicon dies. Therefore, the mechanics of this test is reevaluated in this study by a nonlinear finite element method (NFEM) with considering geometric nonlinearity (or large deflection), associated with related theoretical formulations. The nonlinear mechanics of this test is discussed in detail. NFEM results-based correction factors to the linear beam solutions are further proposed in the form of polynomial fitting equations. Those polynomial fitting equations of the correction factor are proved to be feasible and easy to use with an engineering acceptable accuracy. This correction factor is also found highly dependent on the deflection (δ), span length (L) and radius of roller support (r), but not on test specimen thickness (t) and elastic modulus (E). Finally, the experiments are actually implemented for demonstrating their application.

A 2D finite element (FE) model has been constructed to fast simulating of a typical Chip-On-Film (COF)/Inner Lead Bonding (ILB) process. ANSYS is used to simulations are performed to determine the transient temperature distribution within the PI film, Cu lead and IC chip. The validity of the model is confirmed by comparing the simulation results with the experimental data. The validated model is then used to study tool and stage temperatures which collectively ensure that the interface between the Au bumps and the Sn-plated Cu inner leads achieves the Au-Sn eutectic temperature during the bonding process and therefore forms a strong mechanical joint.

扇出型(Fan-out, FO)封裝廣泛用於手持、移動消費類和物聯網(IoT)等相關應用中，此封裝技術不僅可提供更高的 I/O密度並可經由同質整合(Homogeneous Integration)或異質整合(Heterogeneous Integration)將不同晶片整合在同一個封裝體內。現今扇出型技術發展出幾種不同的封裝結構，例如嵌入式晶圓級 BGA (eWLB)、全模製(Fully-Molded, FM)/ M-Series™和以覆晶技術為主體之Fan-out chip last package (FOCLP) (下圖)等。然而，不同結構間其機械與熱特性之差異並無相關研究進行討論。因此，本文中將利用非接觸式數位影像關係法（Digital Image Correlation, DIC），針對封裝體在不同溫度之翹曲值進行量測與分析，藉以了解封裝體在不同製程溫度下對其之影響，此一量測結果亦可用來驗證有限元素模型之準確性。此外，研究中亦將使用有限元素套裝軟體ANSYS探討不同扇出型封裝結構於機械特性(Warpage, ELK stress, solder ball reliability)與熱阻特性之變化，進而分析其力學基理。

先進電子封裝結構設計需要考慮的設計參數眾多,如封裝元件內部各結構的幾何尺寸、材料性質、接點錫球的尺寸、數量與分布方式等。而傳統以實驗為主的設計方式會耗費大量的成本與時間來完成設計研發，這將影響產品的上市時間並降低其競爭力。半導體相關科技製程日新月異發展迅速，為了縮短研發設計所需的時間及成本，由有限單元法搭配少量驗證用的實驗以取代大量的實驗可大幅縮減開發時間與降低實驗所需的大量成本。然而模擬技術的使用方式與理論選取經常因人而異，不同的研發人員所做的模擬結果都無法一致，因此有必要引入人工智慧中的機器學習方法從實驗認證過的模擬結果資料庫中自動學習各設計參數與結果的關係趨勢，訓練回歸模型並得到一個簡單的預估公式，利用訓練過後得到的公式供研究人員評估先進封裝之可靠度。本研究將以程式語言Python訓練回歸模型，從模型中提取可靠度評估公式，預測在熱循環負載測試下的晶圓級先進封裝結構之可靠度。以有限單元法利用體積權重的概念選定應力集中處之適用網格大小的尺寸劃分，使用Coffin-Manson應變與能量密度壽命預估模型預估錫球的疲勞壽命數，比對數組模擬預測與實驗之誤差需在允許誤差範圍內。在確認模擬使用的模型建構方式、關鍵部位網格大小與非線性力學理論方法之相互搭配確實能有效驗證實驗所獲得的錫球接點壽命，依據此模擬方法代替實驗大量建立不同設計參數的可靠度資料庫供機器學習進行資料訓練，以「人工神經網路(Artificial Neural Network)」、「隨機森林(Random Forest)」、「支援向量回歸(Support Vector Regression)」等機器學習方法從數據中導出最佳回歸模型。本研究發展出來之回歸模型公式將可於設計尺寸範圍內有效推估出封裝結構可靠度，成果將可快速評估晶圓級先進封裝之長時可靠度，可大幅縮減研發時間與研發費用。研究所發展的模擬分析技術、力學理論、設計流程與機器學習設定方法亦可成為各大廠與研發單位之參考，成為未來先進封裝技術發展方向中重要設計依據。